This invention releates to fabrication of semiconductor memory devices, and more particularly to the fabrication of non-volatile memory cell using a single J-FET transistor device.
In order to achieve higher packing density in VLSI technology, the number of device structures for a given area must be minimized. In random access memory, another consideration is to have a minimum number of address lines per cell. The goal of one device per cell is obtained by a structure as disclosed in U.S. patent application Ser. No. 219,023 (J. Hynecke, "High Density JFET RAM Cell," filed Dec. 22, 1980). In this dynamic RAM cell, a single vertical J-FET device is the single memory element. In U.S. patent application Ser. No. 228,413 (R. Bates, "non-volatile J-RAM Cell," filed Jan. 26, 1981), a non-volatile gate feature is added to the vertical J-FET cell.
In the fabrication of a cell of this type, several problems are encountered. The first problem is that the non-volatile elements of the cell may suffer degradation of their memory properties. This is due mainly to processes that are performed on the cell to complete it after the non-volatile elements are in place. Another problem is that of process compatibility between the fabrication of the RAM cells and the MOSFET interface and logic circuits which are built on the same chip.
The present invention is directed to a method of fabrication of a non-volatile (NVJRAM) cell which would have the non-volatile element placed in the device late in the process to avoid deleterious effects due to temperature cycles. Also, the method would accommodate the fabrication of logic circuits on the periphery of a chip to interface the RAM with other elements. The present invention, therefore, has an object of providing a method for fabrication of a non-volatile RAM cell without damage to the memory element. Another object is to provide a method for fabrication of the non-volatile RAM array that will allow interface logic circuits to be constructed on the same chip at the same time.